AMD is gearing up for the release of its next-generation EPYC processors with the new SP7 and SP8 platforms, designed to support the upcoming EPYC ‘Venice’ and ‘Verano’ CPUs. 
These platforms bring significant upgrades, particularly in memory and PCIe support, that promise to revolutionize high-end enterprise and data center markets.
The SP7 platform, aimed at the enterprise segment, will feature up to 16 channels of DDR5 memory. It supports both ECC DDR5 memory with speeds up to 8000 MT/s and MRDIMM memory that can reach up to an impressive 12,800 MT/s in 1DPC configurations. Users will be able to choose from a variety of memory types, including RDIMM, 3DS RDIMM, MRDIMM, and Tall DIMM solutions. On the I/O side, the SP7 platform offers up to 128 PCIe Gen 6.0 lanes, delivering 64 Gbps of bandwidth per lane
. The 2P (dual-socket) version will also feature 16 additional PCIe Gen 4 lanes for expanded I/O flexibility.
The single-socket 1P configuration will support up to 96 PCIe Gen 6.0 lanes, along with 8 additional PCIe Gen 4 lanes. Additionally, the SP7 platform will offer Smart Data Cache Injection (SDCI) to enhance performance further.
The SP8 platform, designed for entry-level solutions, shares many features with the SP7 but with a reduced memory channel configuration of 8 channels. However, the SP8 offers even more PCIe Gen 6.0 lanes, with up to 192 PCIe Gen 6.0 lanes on the 2P platform and 128 PCIe Gen 6.0 lanes on the 1P platform.
Both platforms will support the same types of DDR5 memory but with different channel configurations. The EPYC ‘Venice’ CPUs, powered by the Zen 6C architecture, will offer up to 256 cores and feature 8 CCDs (chiplets) with 128 MB of L3 cache per CCD. This results in a total of 1 GB of L3 cache for the full chip. The Venice CPUs will also include two IO dies, supporting PCIe Gen 6.0, CXL 3.1, DDR5-8000 memory, and more.
For comparison, the current EPYC ‘Turin’ CPUs, based on Zen 5 cores, offer up to 192 cores and 384 threads. The Venice CPUs will push these limits further, with the top-tier models featuring 256 cores and 512 threads, representing a massive leap in processing power for AMD’s EPYC lineup.
The EPYC SP7 processors are expected to have a thermal design power (TDP) around 600W, up from the 400W TDP seen in the Zen 5-based Turin chips. On the other hand, the SP8 chips will have a TDP between 350W and 400W, offering a balance of power efficiency and performance.
As we look ahead, these EPYC Venice and Verano CPUs, launching in 2026 and 2027 respectively, will likely play a critical role in shaping the future of data centers, offering massive improvements in memory bandwidth, core counts, and PCIe capabilities.
1 comment
Zen 7 might stack all the L3 cache which could mean stacked chips for AMD’s gaming SKUs. Would be awesome to see that!